1. Field of the Invention
The present invention relates to a semiconductor chip package, and in particular, to a semiconductor chip stack package and fabrication method having a plurality of heat sinks.
2. Background of the Related Art
FIGS. 1A and 1B show related art semiconductor chip stack packages. FIG. 1A shows a two-chip stacked semiconductor package, and FIG. 1B shows a three-chip stacked semiconductor package. A plurality of semiconductor chips 2 are stacked on a semiconductor substrate interposing an insulating adhesive 3. Chip pads (not shown) on the semiconductor chips 2 are respectively connected via a corresponding one of a plurality of conductive wires 4 to the semiconductor substrate 1.
The related art chip package structures make a stack package structure by stacking a plurality of semiconductor chips one atop another. However, the related art stack package becomes undesirably large in size because of the wire loops. Thus, a minimal size package is difficult to obtain using the related art structures.
FIG. 2 shows a cross-sectional view of another related art semiconductor chip stack package that includes a plurality of bumps 11 formed on each side portion of the surfaces of respective semiconductor chips 10, 10'. The bumps 11 can be respectively coupled to a corresponding one of a plurality of inner leads 12. The plurality of inner leads 12 extend to an outer lead 13. A predetermined area of the package including the semiconductor chips 10, 10' and the inner leads 12 is molded by an epoxy molding compound 14.
The stack package shown in FIG. 2, however, has a disadvantage because the semiconductor package chips 10, 10' emit significant heat during operation, but discharge the heat through the outer leads 13. The heat discharge by the chips 10, 10' is not sufficient, which deteriorates package reliability.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.